1. Field of the Invention
This invention relates to integrated semiconductor memory circuits and more particularly to memory circuits which employ a capacitor for storing binary digits of information.
2. Description of the Prior Art
Integrated semiconductor memory circuits, particularly those employing cells which include essentially a storage capacitor and a switch, have achieved high memory cell densities. One of the simplest circuits for providing small memory cells is described in commonly assigned U.S. Pat. No. 3,387,286, filed July 14, 1967, by R. H. Dennard. Each of these cells employs a storage capacitor and a field effect transistor acting as a switch to selectively connect the capacitor to a bit/sense line. In also commonly assigned U.S. Pat. Nos. 3,811,076, by W. M. Smith, and 3,841,926 by R. H. Garnache and W. M. Smith, both filed Jan. 2, 1973, there is disclosed a one device field effect transistor memory cell of the type described in the above identified Dennard patent which is fabricated to a very small size by utilizing a layer of doped polycrystalline silicon separated by a dielectric medium disposed on the surface of a semiconductor substrate for forming a storage capacitor.
In commonly assigned U.S. Pat. No. 3,979,734, filed on June 16, 1975, by W. D. Pricer and J. E. Selleck, there is described a fast memory array made of small cells which employ storage capacitors and bipolar transistors. In this latter array, which is word organized, each storage capacitor of these cells has simply one capacitor terminal connected to a separate bit/sense line while selected cells forming a word are simultaneously accessed by utilizing a word pulse for coupling to the other terminal of the storage capacitors of that word. The bipolar transistors require a more complex fabrication process than do the field effect transistors.
Memory arrays utilizing cells which employ two active devices and provide a preamplified signal to a bit/sense line are also known but when such known cells are used they produce a very complex memory array generally requiring a large semiconductor surface area. A two device memory cell described in U.S. Pat. No. 3,882,472, filed May 30, 1974, requires two lines to address the word and means must be provided to keep track of whether the data stored in the cells is true or inverted. Another two device memory cell is described in U.S. Pat. No. 3,614,749, filed June 2, 1969. In this latter patent two word lines and two bit lines are required, as well as area-consuming contacts between a gate electrode of one transistor and a current-carrying electrode of the second transistor. A third memory cell utilizing two devices is taught in commonly assigned U.S. Pat. No. 3,919,569, filed Dec. 29, 1972. The cell described in this latter patent uses complementary transistors and requires two bit lines.
The three device memory cell, such as disclosed in commonly assigned U.S. Pat. No. 3,585,613, filed Aug. 27, 1969, also provides a preamplified signal to a bit/sense line but the three devices consume a substantial amount of surface area of the semiconductor substrate and require two word lines.